The present invention relates to computer graphics, and more particularly to interactive graphics systems such as home video game platforms. Still more particularly this invention relates to a memory controller for use in such an interactive graphics system that controls resource access to main memory.
Many of us have seen films containing remarkably realistic dinosaurs, aliens, animated toys and other fanciful creatures. Such animations are made possible by computer graphics. Using such techniques, a computer graphics artist can specify how each object should look and how it should change in appearance over time, and a computer then models the objects and displays them on a display such as your television or a computer screen. The computer takes care of performing the many tasks required to make sure that each part of the displayed image is colored and shaped just right based on the position and orientation of each object in a scene, the direction in which light seems to strike each object, the surface texture of each object, and other factors.
Because computer graphics generation is complex, computer-generated three-dimensional graphics just a few years ago were mostly limited to expensive specialized flight simulators, high-end graphics workstations and supercomputers. The public saw some of the images generated by these computer systems in movies and expensive television advertisements, but most of us couldn't actually interact with the computers doing the graphics generation. All this has changed with the availability of relatively inexpensive 3D graphics platforms such as, for example, the Nintendo 64® and various 3D graphics cards now available for personal computers. It is now possible to interact with exciting 3D animations and simulations on relatively inexpensive computer graphics systems in your home or office.
In generating exciting 3D animations and simulations on relatively inexpensive computer graphics systems, it is important to efficiently control access to main memory among competing resources. Any such access control system is burdened with considerable constraints. For example, the main application program executing CPU, which is but one of many resources seeking access to main memory, must be granted memory access with a fixed memory read latency allowing for high speed execution of instructions. Accordingly, such a CPU should be awarded high priority access to main memory. In order to generate exciting graphics, certain graphics related resources seeking memory access must likewise be guaranteed high speed access to memory sufficient for the graphics processing to be rapidly completed.
The present invention is embodied in the disclosed illustrative memory controller described herein, which performs a wide range of memory control related functions including arbitrating between various competing resources seeking access to main memory. Other tasks performed by the unique memory controller include handling memory latency and bandwidth requirements of the resources requesting memory access, buffering writes to reduce turn around, refreshing main memory, protecting main memory using programmable registers, and numerous other functions.
In controlling memory access between resources seeking to read from and write to main memory, the memory controller minimizes switching between memory reads and memory writes to avoid wasting memory bandwidth due to idle cycles resulting from such switching and thereby enhancing memory access time. The illustrative memory controller minimizes such switching by incorporating a unique write buffering methodology that uses a “global” write queue which queues write requests from various diverse competing resources to reduce read/write switching. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained.
The memory controller in accordance with the illustrative embodiment described herein, advantageously optimizes access to main memory taking into account resource memory latency and bandwidth requirements.
The memory controller described herein uniquely resolves memory coherency issues to avoid accessing stale data from memory due to reading data from a main memory address location prior to when that same location had been updated by a write operation. Coherency issues are addressed both within a single resource that has both read and write capability and difference resources. The exemplary embodiment addresses such coherency issues by efficiently flushing buffers associated with a resource. For example, a resource that is writing to main memory may send a flush signal to the memory controller to indicate that the resource's write buffer should be flushed. In accordance with an exemplary implementation, the memory controller generates a flush acknowledge handshake signal to indicate to competing resources that data written to main memory is actually stored in main memory rather than in an associated resource buffer.